1. Field of the Invention
The present invention relates to a method of controlling a drive source such as a motor by use of an output from an encoder coupled to or provided to be integral with the drive source, and particularly to a method of controlling a drive source so that the drive source can be driven to keep at a constant speed.
2. Description of the Related Art
A conventional method of controlling a drive source will be described with reference to FIG. 14.
FIG. 14 is a block diagram showing the outline of the conventional method of controlling a drive source. Referring to FIG. 14, there are shown a drive source 1 such as a DC motor, and an encoder 2 provided on a shaft of the drive source 1 so that the encoder can generate a pulse each time the drive source 1 rotates by a certain angle. There are also shown an A-phase signal 3a from the encoder 2, and a B-phase signal 3b from the encoder 2. The phases A and B of those signals are generally designed to be shifted by 90.degree., but sometimes have error of about ten or more percent. In addition, the duty ratio of each phase signal is designed to be 50%, but sometimes has error of about ten and several percents. There are shown edge detectors 4a, 4b, which detect the leading edge and trailing edge of each of the A-phase and B-phase signals 3a, 3b to produce pulses. A rotation direction detector 5 detects the rotation direction of the drive source 1 according to the state (Low or High) of the B-phase signal 3b when the leading edge of the A-phase signal 3a is detected, for example.
A composing circuit 6 calculates the logical sum, OR of the outputs from the edge detectors 4a, 4b to produce pulses which includes all the pulses generated by detecting the leading and trailing edges of each of the A-phase and B-phase signals 3a, 3b. An up/down counter 7 counts up or down the pulse from the composing circuit 6 in accordance with the output of the rotation direction detector 5. The object to be driven by the drive source 1 can be detected in its position by referring to the output of the up/down counter 7. A prescaler 8 divides its input signal at a desired rate. A selector 9 can select one of the outputs of the prescaler 8 and encoder 2. There are also shown a central processing unit (hereinafter, abbreviated "CPU") 10, a clock generator 11 for generating a clock signal to the CPU 10, a motor driver 12 which controls the rotation speed of the drive source 1 on the basis of a control signal produced from the CPU 10.
With reference to FIGS. 14 and 15, a detailed description will be made of the process in which the CPU 10 obtains the speed information of the drive source 1. In FIG. 15, reference numeral 13 denotes the output signal of the selector 9; 14a, 14b, 14c and 14d the leading edges of the selector output signal 13; and 15ab, 15bc and 15cd the time intervals between the leading edges 14a and 14b, between the leading edges 14b and 14c, and between the leading edges 14c and 14d. In addition, reference numeral 16ab, 16bc and 16cd denote the count values about the clock signal (described later) in the time intervals 15ab, 15bc and 15cd. Reference numerals 17b, 17c and 17d denote the interruption requests to the CPU 10.
The CPU 10 measures the intervals between the leading edges of the selector output signal 13, or the time intervals 15ab, 15bc and 15cd by counting the clock signal produced from the clock generator 11. The CPU 10 includes a built-in counter (not shown) for this purpose, and a built-in register (not shown) for holding the count value of the built-in counter.
The built-in counter is a free-run counter which is incremented each time it receives the clock pulse from the clock generator 11, and thus increases its count value with lapse of time.
When the leading edge of the selector output signal 13 is applied to the CPU 10, the count value of the counter which has counted the number of clock pulses is copied in the built-in register, and the count value of the counter is reset to zero. For example, the count value 16ab resulting from counting the clock signal in the time interval 15ab is held in the built-in register, and the count value of the built-in counter is immediately reset to zero. After resetting, the counter is incremented each time it receives the clock signal, and the count value 16ab stays copied in the built-in register.
The interruption request to the CPU 10 occurs at the leading edge. If the interruption request 17b to the CPU 10 occurs at the leading edge 14b, the CPU 10 reads out the count value held in the built-in register, for example. At this time, the current count value is the count value 16ab resulting from measuring the time interval 15ab. Since the count value 16ab is held in the built-in register until the next leading edge 14c comes, it can be easily obtained even by relatively slow interruption processing using software. Similarly, the CPU 10 can obtain the count value 16bc corresponding to the time interval 15bc when the interruption request 17c occurs at the leading edge 14c, and the count value 16cd corresponding to the time interval 15cd when the interruption request 17d occurs at the leading edge 14d.
If the drive source 1 is rotated at equal speed, the leading edges 14a, 14b, 14c and 14d of the output signal 13 occur at equal distances, and thus the time intervals 15ab, 15bca and 15cd are equal, so that the count values 16ab, 16bc and 16cd become all equal. However, if the rotation speed of the drive source 1 changes, the count values 16ab, 16bc and 16cd about the clock signal change according to the speed of the drive source 1 as shown in FIG. 15. If the speed of the drive source 1 is reduced, the interval between the leading edges of the selector output signal 13 becomes wide, leading to the increase of the count value. On the contrary, if the speed of the drive source 1 is increased, the interval between the leading edges of the output signal 13 becomes narrow, leading to the decrease of the count value. Therefore, the speed of the drive source 1 can be measured by the count value.
A detailed description will be made of the process in which the obtained count value is converted into the speed information.
The encoder signal is a signal indicating the "distance" generated each time the drive source (e.g. a motor) rotates by a predetermined angle. In addition, since the count value resulting from counting the clock signal indicates "time," the CPU 10 is able to produce the speed information of the drive source 1 by computing the "distance" divided by the "time." Since the "distance" can be considered to be constant in view of the property of the encoder, a proper value is defined as a speed conversion constant, and the speed conversion constant divided by the count value is calculated, so that the speed information can be obtained.
A detailed description will be made of the process in which the control signal is generated on the basis of the obtained speed information.
In order to obtain the final control signal, it is necessary to provide a control target as a guide of how the object to be controlled is controlled. Under speed control, it is ideal that the drive source is operated at a constant speed, and at this time the edge interval of the selector output signal 13 is decided by designing the drive system. Also, the frequency of the clock signal for use in counting the edge period is similarly decided during the design stage. Therefore, the count value (theoretical count value) of the built-in counter in the ideal state is also decided when the drive system is designed. Since the speed conversion constant is constant as described above, the ideal speed information (target speed) is decided to be equal to the speed conversion constant divided by the theoretical count value, and thus becomes naturally a constant value. The object of the control is to make the measured speed information equal to the theoretical speed. If this state can be assured, the system is ideally driven.
FIG. 16 is a flowchart of the conventional process for generating the control signal. The conventional example employs PI control. The PI control is a process using terms of P (proportional) and I (integral), and is also called proportional integration control. This control is a very popular feedback control process.
At step 1, speed deviation e is calculated according to the following equation (1). EQU (speed deviation e)=(target speed)-(speed information) (1)
At step 2, the speed deviation e obtained at step 1 is accumulated (integrated) as shown by the following equation (2) to produce EQU (distance deviation)=.SIGMA.e (2)
At step 3, a speed command value is calculated using the speed deviation and the distance deviation according to the following equation (3). EQU (speed command value)=K{(speed deviation)+(distance deviation)/T}(3)
The proportional integration control includes two coefficients of K and T, of which K is called a proportional coefficient, and T is called an integration coefficient. These coefficients depend on the hardware (motor, motor driver and so on) which constitutes the drive system, and are determined by a method of analog simulation by SPICE and so on, or limited sensitivity.
A method of changing the speed of the object to be controlled in the prior art will be described with reference to FIG. 14. For simplicity, the speed of the drive system is assumed to be a reference speed V when the CPU 10 selects the output directly from the encoder 2 as the selector output signal 13.
Let us consider that the drive speed is changed to 2.times.V. The CPU 10 sets the prescaler 8 to divide the input signal by two, and orders the selector 9 to select the output of the prescaler 8. Thus, the leading edges are supplied to the CPU 10 with twice (frequency=1/2) as long as the period at which the speed of the drive system is V. If the speed remains the reference speed V, the count value of the built-in counter of the CPU 10 is twice as large as that at the reference speed V, but the CPU 10 controls the drive source so that the count value of the built-in counter is constant. As a result, the speed of the drive source is 2.times.V. In other words, the edge period of the selector output signal 13 at the reference speed V is equal to that at the speed 2.times.V. Plainly speaking, (speed).times.(prescaler division ratio)=constant. However, since the amount of difference per time in the drive system is increased with the increase of speed, the loop gain of the control system must be changed in accordance with speed. Specifically, the proportional coefficient K mentioned with reference to FIG. 16 is increased or decreased according to speed. If the speed is 2.times.V, the coefficient K is multiplied by two as is the speed, thus compensating the loop gain.
The relation between the drive speed an d the encoder output will be described with reference to FIG. 17. In FIG. 17, the small circles .smallcircle. indicate the controlled points of the drive source by the CPU 10.
According to the above method, when the drive speed is controlled to be higher than the reference speed V ((c) of FIG. 17), the encoder signal is simply thinned by the prescaler 8. For example, the drive speed is changed to twice the reference speed V by thinning the encoder signal to 1/2 ((b) of FIG. 17), and to four times the reference speed V by thinning the encoder signal to 1/4 ((a) of FIG. 17), with the service period of the CPU 10 being constant as indicated by the small circles .smallcircle..
However, since the encoder signal cannot be increased, the speed cannot be easily controlled to be slower than the reference speed V. The small squares .quadrature. in (d) and (e) of FIG. 17 indicate the controlled points at which no service can be executed by the CPU 10. For example, when the speed is 1/2.times.V, the number of times that the CPU 10 can offer control/arithmetic service is reduced to 1/2 ((d) of FIG. 17) and to 1/4 ((e) of FIG. 17) that at the time of the reference speed V. The reduction of the number of times of service directly results in the reduction of control performance, particularly of servo band.
There is a method shown in FIG. 18 as a counter-measure against that, for example. FIG. 18 is a diagram showing a method of simply increasing the number of times that the CPU 10 can offer service. In FIG. 18, the small circles .smallcircle. indicate edges at which the CPU 10 offers service. When the drive speed is the reference speed V, the CPU 10 executes control operation using the one-side edges of the single-phase signal (for example, A-phase) from the encoder 2. When the drive speed is 1/2 the reference speed V, the CPU 10 controls using the both-side edges of the single-phase signal (for example, A-phase) from the encoder 2. When the drive speed is 1/4 the reference speed V, the CPU 10 controls using the both-side edges of the two-phase signals (A-phase, B-phase) from the encode 2.
This method is able to very simply assure the number of times that the CPU 10 offer service. However, originally the servo operation is performed under the condition that the edge interval (=distance) of the signal from the encoder 2 is always kept constant, whereas the above method sometimes cannot satisfy this condition.
The case of unequal edge distance will be described with reference to FIGS. 19A and 19B.
FIG. 19A shows the different phase-signals of the encoder 2 each of which has a duty ratio of 50% and a phase difference of 90.degree.. FIG. 19B shows the different phase-signals with a disturbed phase relation different from the state shown in FIG. 19A because of, for example, low precision of encoder 2. In FIG. 19A, when the drive source is ideally driven, the four intervals (interval A: between the leading edge of A-phase and the leading edge of B-phase, interval B: between the leading edge of B-phase and the trailing edge of A-phase, interval C: between the trailing edge of A-phase and the trailing edge of B-phase, and interval D: between the trailing edge of phase-B and the leading edge of phase-A) are all equal. Thus, the edge intervals are equal if all edges of the two-phase signals are obtained.
However, in FIG. 19B, since the duty ratio is not 50% and the phase difference is not 90.degree., the four intervals A', B', C' and D' produced by the two A-and B-phase signals are different from each other. Even if the drive source is driven ideally, the edge intervals formed at the variable points of each phase signal are not equal.
Since the servo operation is performed under the condition that the edge intervals (=distances) of the phase signals of the encoder 2 are always equal as described above, the control signal produced as the result of arithmetic operation in the state shown in FIG. 19B oscillates with the period of interval A, interval B, interval C and interval D as one cycle. Therefore, the drive source generates abnormal sound coincident with the oscillation period, and the operation of all the control system becomes unstable.
Most commercially available encoders exhibit such the characteristic as shown in FIG. 19B, and there are even some encoders which generate phase signals of which the phase difference and duty ratio have error of ten or more percent.
The conventional drive source controlling method mentioned above has the following problems. When the speed of the drive source is controlled to be slower than the reference speed V, the resolution of the encoder is relatively reduced, so that it is difficult to assure the control band. Since the edge intervals of signals from the encoder become wider as the drive source speed decreases as shown in FIG. 18, fast response cannot be expected when the system speed changes. In general, the reciprocal (frequency) of the period of the leading edges is the sampling rate. When the sampling rate is reduced, the number of times of service is reduced, and the control performance of the servo system is deteriorated.
Although a high-resolution encoder can be used, the high-resolution encoder is generally very expensive, and thus increases the cost.
In addition, since the encoder produces signals of A- and B-phase, it is theoretically possible to assure four times as high as the sampling rate of the prior art by, for example, detecting the both-side edges of both the A-phase signal and the B-phase signal, and by obtaining the speed information and controlling on the basis of this detected timing according to the above method. However, as described in detail with reference to FIGS. 19A and 19B, the duty ratio and phase difference of the difference phase signals of the encoder scatter within the range of ten or more percent, and thus reliance cannot be placed on the information which is to show a constant interval. If controlling is made in disregard of this fact, abnormal sound will be generated from the drive source or the operation of the control system will become unstable.